1. Field of the Invention
The present invention relates to a differential circuit and a multiplier and more particularly, to a differential circuit having an ideal linear behavior with respect to an input signal, and a multiplier using the differential circuit, which is preferably formed on a semiconductor integrated circuit (IC).
2. Description of the Prior Art
A conventional differential circuit using a logarithmic converter is shown in IEEE Journal of Solid-State Circuits, Vol. SC-3, No.4, December 1968, pp 365-373, entitled "A Precise Four-Quadrant Multiplier with Subnanosecond Response", which was written by Barrie Gilbert.
The logarithmic conversion of the converter is realized on the basis of the following fact.
Supposing that the base-width modulation (i.e., the Early voltage) is ignored, the collector current I.sub.C and the base-to-emitter voltage V.sub.BE typically has the following relationship (1). ##EQU1##
In the equation (1), I.sub.s is the saturation current of the transistor, and V.sub.T is the thermal voltage defined as EQU V.sub.T kT/q (2)
where k is the Boltzmann's constant, T is absolute temperature in degrees Kelvin, and q is the charge of an electron.
It is seen from the equation (1) that the logarithmic conversion is able to be realized by the use of the above relationship (1).
The multiplier disclosed in the above article is shown in FIG. 1, which corresponds to the circuit of FIG. 8 in the article. In FIG. 1, the reference numeral 61 indicates the well-known Gilbert multiplier cell, the reference numeral 62 indicates a logarithmic converter as an input circuit for the multiplier cell 61, the reference numeral 65 indicates emitter-degeneration resistors, and the reference numeral 85 indicates load resistors of the multiplier cell 61.
The logarithmic conversion of the input circuit 62 is performed by the use of the equation (1). Specifically, two bipolar transistors 71 and 72 constitute an emitter-coupled pair, and two diode-connected bipolar transistors 73 and 74 serve as loads for the respective transistors 71 and 72. A differential input voltage X is applied across bases of the transistors 71 and 72. Two output voltages of the input circuit 62 are derived from the collectors of the transistors 71 and 72.
the collector current and the base-to-emitter voltage have the above relationship (1) and therefore, the two output voltages are equal to the logarithmically converted voltages of the input voltage X, respectively. These two output voltages are applied across bases of bipolar transistors 77,80 and 78,79 of the multiplier cell 61.
An input voltage Y is differentially applied across bass of bipolar transistors 75 and 76.
The multiplication result X.multidot.Y of the input voltages X and Y is differentially derived through the load resistors 85.
On the other hand, the combination of the Gilbert multiplier cell and a predistortion circuit was created by B. Gilbert, which has been termed the "Gilbert multiplier" and includes two "Gilbert gain cells". A differential circuit serving as the Gilbert gain cell is shown in FIG. 2.
As shown in FIG. 2, bipolar transistors Q101 and Q102 whose emitters are coupled together through an emitter resistor (resistance :R) form a differential pair of an input circuit. Two diode-connected bipolar transistors Q103 and Q104 constitute loads of the differential pair of the transistors Q101 and Q102. The transistors Q101 and Q102 are driven by constant currents I.sub.0, respectively.
Bipolar transistors Q105 and Q106 whose emitters are coupled together form a differential pair of the Gilbert gain cell. The transistors Q105 and Q106 are driven by a common constant current I.sub.1.
An input voltage V.sub.i is applied across bases of the transistors Q101 and Q102. Collector currents of the transistors Q101 and Q102 vary according to the change of the input voltage V.sub.i. The change of the collector currents are derived through the load transistors Q103 and Q104 to thereby generate a logarithmically-compressed output voltage V.sub.o between the collectors of the transistors Q101 and Q102.
The logarithmically-compressed output voltage V.sub.o ' is then applied across bases of the transistors Q105 and Q106. The differential pair of the transistors Q105 and Q106 amplifies voltage V.sub.o to generate a differential output current .DELTA.I.sub.C between collectors of the transistors Q105 and Q106.
As described above, in the Gilbert gain cell, the diode-connected transistors Q103 and Q104 serving as the loads for the transistors Q101 and Q102 constitute a predistortion circuit for the transistors Q105 and Q106.
In the differential circuit of FIG. 2, when a current flowing through the emitter resistor of the transistors Q101 and Q102 and base-to-emitter voltages thereof are defined as i, V.sub.BE1 and V.sub.BE2, respectively, the following equation (3) is established. EQU V.sub.t =V.sub.BE1 -V.sub.BE2 +Ri (3)
Here, supposing that (Ri&gt;&gt;V.sub.BE1 -V.sub.BE2) is established, the following equation (4) is obtained. ##EQU2##
The current if lows through the load transistors Q103 and Q104 as a differential current. The inter-terminal voltage V.sub.o of the diode-connected transistors Q103 and Q104 is equal to a voltage obtained by logarithmically compressing the input voltage V.sub.i. The output voltage C.sub.o of the differential pair of the transistors Q101 and Q102 is then exponentially expanded and amplified by the differential pair of the transistors Q105 and Q106, thereby generating the differential output current .DELTA.UI.sub.C. The differential output current .DELTA.I.sub.C caries proportionally to the current i and the input voltage V.sub.i.
With the conventional differential circuit of FIG. 2, since an approximation is performed by the use of the equation (4), a problem that the differential output current .DELTA.I.sub.C does not vary completely proportional to the differential input voltage V.sub.i occurs. In other words, the conventional differential circuit of FIG. 2 has a problem that it does not perform a completely (or, ideal) linear behavior with respect to the differential input voltage V.sub.i.